VHDL/Słowa kluczowe
< VHDL
begin end type is signal variable alias entity architecture process component downto to port map in out inout buffer constant subtype range units array of record not and or if then elsif for while switch case where
begin end type is signal variable alias entity architecture process component downto to port map in out inout buffer constant subtype range units array of record not and or if then elsif for while switch case where